A fully digital power supply noise thermometer

Power Supply Noise (PSN) is one of the main concerns in scaled technology circuits, both if performance reliability must be assured and if power supply is to be dynamically reduced for dissipation regulation. In this paper we propose a new system for digitally sensing Power Supply and Ground levels that can be both transferred to the output for verification purposes and used by a control block within the circuit under test (CUT) for the activation of power aware policies. The sensor system shows very low overhead in terms of power and area, and works at the nominal CUT frequency. It allows to change on-site the Power Supply and Ground ranges to be sensed and, after a fine tuning, can be arranged for a process variation aware measures. This sensor is fully digital and standard cell based and can be used for every type of architecture on a systematic basis for PSN measure as scan chains are for fault verification. It thus represents a change of paradigm in the way in which PSN measure systems are thought nowaday

A Technology Aware Magnetic QCA NCL-HDL Architecture

Magnetic Quantum Dot Cellular Automata (MQCA) have been recently proposed as an attractive implementation of QCA as a possible CMOS technology substitute. Marking a difference with respect to previous contributions, in this work we show that it is possible to develop and describe complex MQCA computational blocks strongly linking technology and having in mind a feasible realization. Thus, we propose a practicable clock structure for MQCA baptised "snake-clock", we stick to this while developing a system level Hardware Description Language (HDL) based description of an architectural block, and we suggest a delay insensitive Null Convention Logic (NCL) implementation for the magnetic case so that the "layout=timing" problem can be solved. Furthermore we include in our model aspects critically related to technology and real production, that is timing, power and layout, and we present the preliminary steps of our experiments, the results of which will be included in the architecture descriptio

NanoMagnet Logic: an Architectural Viewpoint

Among the possible implementation of Field- Coupled devices NanoMagnet Logic is attractive for its low power consumption and the possibility to combine memory and logic in the same device. However, the nature of these technologies is so different from CMOS transistors that the implications on the circuit architecture must be taken carefully into account. In this work we analyze the most important issues related to the design of complex circuits using this technology. We discuss how they influence the architectural level. We propose detailed solutions to solve these problems and to improve the overall performance. As a result of this analysis the type of circuits and applications that constitute the best target for this technology are identified. The analysis is performed on NanoMagnet Logic but the results can be applied to any QCA technolog

A VHDL-AMS Simulation Environment for an UWB Impulse Radio Transceiver

Ultra-Wide-Band (UWB) communication based on the impulse radio paradigm is becoming increasingly popular. According to the IEEE 802.15 WPAN Low Rate Alternative PHY Task Group 4a, UWB will play a major role in localization applications, due to the high time resolution of UWB signals which allow accurate indirect measurements of distance between transceivers. Key for the successful implementation of UWB transceivers is the level of integration that will be reached, for which a simulation environment that helps take appropriate design decisions is crucial. Owing to this motivation, in this paper we propose a multiresolution UWB simulation environment based on the VHDL-AMS hardware description language, along with a proper methodology which helps tackle the complexity of designing a mixed-signal UWB System-on-Chip. We applied the methodology and used the simulation environment for the specification and design of an UWB transceiver based on the energy detection principle. As a by-product, simulation results show the effectiveness of UWB in the so-called ranging application, that is the accurate evaluation of the distance between a couple of transceivers using the two-way-ranging metho

Compact Model for Multiple Independent Gates Ambipolar Devices

The model presented is a charge-based model that assures the continuity of the current and the analytical derivability of charges to obtain the parasitic capacitances. It has been conceived to support the multiple independent gates, typical of nano-array structures, where each gate controls the charge in the channel. Charge conservation implies constant current in the different section of the multiple gate nanowire FET, making possible the development of a compact model for an arbitrary number of gates. The model has been used to describe different structures (i.e. number of gates, dimension of the single transistor and ranges of applied voltages) under static conditions and the results have been verified on Silvaco TCAD simulations. The modeling approach and the attained results for some cases of study will be presented and discusse

NanoMagnetic Logic Microprocessor Hierarchical Power Model

The interest on emerging nanotechnologies has been recently focused on NanoMagnetic Logic (NML), which has unique appealing features. NML circuits have a very low power consumption and, due to their magnetic nature, they maintain the information safely stored even without power supply. The nature of these circuits is highly different from the CMOS ones. As a consequence, to better understand NML logic, complex circuits and not only simple gates must be designed. This constraint calls for a new design and simulation methodology. It should efficiently encompass manifold properties: 1) being based on commonly used hardware description language (HDL) in order to easily manage complexity and hierarchy; 2) maintaining a clear link with physical characteristics 3) modeling performance aspects like speed and power, together with logic behavior. In this contribution we present a VHDL behavioral model for NML circuits, which allows to evaluate not only logic behavior but also power dissipation. It is based on a technological solution called ``snake-clock''. We demonstrate this model on a case study which offers the right variety of internal substructures to test the method: a four bit microprocessor designed using asynchronous logic. The model enables a hierarchical bottom-up evaluation of the processor logic behavior, area and power dissipation, which we evaluated using as benchmark a division algorithm. Results highlight the flexibility and the efficiency of this model, and the remarkable improvements that it brings to the analysis of NML circuit

Energy Detection UWB Receiver Design using a Multi-resolution VHDL-AMS Description

Ultra Wide Band (UWB) impulse radio systems are appealing for location-aware applications. There is a growing interest in the design of UWB transceivers with reduced complexity and power consumption. Non-coherent approaches for the design of the receiver based on energy detection schemes seem suitable to this aim and have been adopted in the project the preliminary results of which are reported in this paper. The objective is the design of a UWB receiver with a top-down methodology, starting from Matlab-like models and refining the description down to the final transistor level. This goal will be achieved with an integrated use of VHDL for the digital blocks and VHDL-AMS for the mixed-signal and analog circuits. Coherent results are obtained using VHDL-AMS and Matlab. However, the CPU time cost strongly depends on the description used in the VHDL-AMS models. In order to show the functionality of the UWB architecture, the receiver most critical functions are simulated showing results in good agreement with the expectations